Tobias Massier
Publications

Publication details

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

Publication data

Type:
Journal article
Authors:
Tobias Massier, Helmut E. Gräb and Ulf Schlichtmann
Published in:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 12
Electronic ISSN: 1937-4151, Print ISSN: 0278-0070
Impact factor: 2.7 (2024)
Publisher:
Institute of Electrical and Electronics Engineers (IEEE), New York (New York, United States of America)
Publication date:
December 2008
Pages:
2209–2222
Abstract:
This paper presents the sizing rules method for basic building blocks in analog CMOS and bipolar circuit design. It consists of the development of a hierarchical library of transistor-pair groups as basic building blocks for analog CMOS and bipolar circuits, the derivation of a hierarchical generic list of constraints that must be satisfied to guarantee the function and robustness of each block, and the development of a reliable automatic recognition procedure of building blocks in a circuit schematic. Sizing rules efficiently capture design knowledge on the technology-specific level of transistor-pair groups. This reduces the effort and improves the resulting quality for analog circuit synthesis. Results of applications like circuit sizing, design centering, response surface modeling, or analog placement show the benefits of the sizing rules method.
Keywords:
Analog circuits, CMOS transistors, Bipolar transistors, Circuit sizing, Circuit synthesis, Optimisation, Circuit topology, Structural analysis
DOI:

Further information

Recognition:
The method presented in this paper was implemented in two commercial software tools for circuit simulation and electronic design automation.

Resources

Version of record  (external link) Accepted manuscript  (download)
Go back to the previous page
Format: 
@article{Massier_SizingRulesMethod_2008,
  author    = {Massier, Tobias and Gr{\"a}b, Helmut E. and Schlichtmann, Ulf},
  title     = {The Sizing Rules Method for {CMOS} and Bipolar Analog Integrated Circuit Synthesis},
  year      = {2008},
  month     = dec,
  journal   = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  issn      = {1937-4151},
  publisher = {IEEE},
  address   = {New York, NY, US},
  volume    = {27},
  number    = {12},
  pages     = {2209--2222},
  doi       = {10.1109/TCAD.2008.2006143},
  keywords  = {Analog circuits, CMOS transistors, Bipolar transistors, Circuit sizing, Circuit synthesis, Optimisation, Circuit topology, Structural analysis},
}
@article{Massier_SizingRulesMethod_2008,
  author       = {Massier, Tobias and Gr{\"a}b, Helmut E. and Schlichtmann, Ulf},
  title        = {The Sizing Rules Method for {CMOS} and Bipolar Analog Integrated Circuit Synthesis},
  date         = {2008-12},
  journaltitle = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  issn         = {1937-4151},
  publisher    = {IEEE},
  location     = {New York, NY, US},
  volume       = {27},
  number       = {12},
  pages        = {2209--2222},
  doi          = {10.1109/TCAD.2008.2006143},
  keywords     = {Analog circuits, CMOS transistors, Bipolar transistors, Circuit sizing, Circuit synthesis, Optimisation, Circuit topology, Structural analysis},
}
Copied✓
⇧